1. Field of the Invention
This invention relates to flash EEPROM memory arrays, and more particularly, to methods and apparatus for storing control information used in programming and reading advanced flash EEPROM memory arrays which are capable of storing more than one bit of data in each memory cell.
2. History of the Prior Art
Recently, flash electrically-erasable programmable read only memory (flash EEPROM memory) has been used as a new form of long term storage. A flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. The memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. The charge level may be detected by interrogating the devices. Flash EEPROM memory arrays may be designed to provide a smaller lighter functional equivalent of a hard disk drive which operates more rapidly and is not as sensitive to physical damage. Flash EEPROM memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important.
As originally devised, each flash EEPROM memory device stores a single bit of data. If a flash EEPROM memory device is programmed so that a significant charge is stored on the floating gate, the state is typically referred to as a "zero" or programmed state; while if little or no charge is stored on the gate, this is typically considered a "one" or erased state. Recently, it has been discovered that the transistor devices used for flash EEPROM memory arrays may be made to store charge at a number of discrete levels greater than the charge level of the erased state. Essentially, more than two discrete levels of charge (including the erased level) may be stored on the floating gates of the devices during programming and erasing by varying the voltages applied to the terminals of the devices and the duration of application; and these different charge levels (device conditions or states) may be detected. This allows flash EEPROM devices in memory arrays to store more than one bit per device and radically increases the storage capacity of such arrays. A device used in this manner is referred to as a multi-bit cell.
There are a number of problems which arise from the storage of more than one bit of data by a flash EEPROM cell. Because the maximum charge which may be stored on the floating gate is essentially fixed for any particular memory device, the differences between charge levels which indicate the different data values stored by the device are much smaller when a number of levels are stored. The different charge levels are sensed by comparison to charge levels stored by reference cells. Over time, charge tends to leak from the floating gates of the memory devices. What would be relatively minor leakage from the floating gate of a device storing only a single bit of data may change the charge level sufficiently to produce an incorrect value for comparison to a reference charge level in a device arranged to store a number of different charge levels. Consequently, there is chance for more errors to be caused by charge leakage from the floating gates of individual flash EEPROM devices arranged to store a number of different charge levels.
This increase in errors has a deleterious effect beyond what might be expected on flash EEPROM memory arrays. In one embodiment of long term flash EEPROM memory, the memory array is divided into a plurality of blocks the cells of each of which are erased simultaneously. Within these blocks, data sets are stored of a size usually much smaller than that of a block of flash EEPROM memory. In one embodiment, these data sets are stored in sectors of a size matching those of a typical electro-mechanical hard disk drive. With each of these data sets is stored some control information used primarily for correctly reading or writing the data set. It is necessary that this control information be correctly stored and retrieved so that data may be accurately written and retrieved from a flash EEPROM memory array.
In order to preserve the validity of data and allow the storage of more than one bit per memory device, error detection and correction (EDC) codes may be stored with the data stored in each data set in a flash EEPROM memory array. This error detection and correction code allows correction to be made to data which has failed due to leakage or other cell problems. Unfortunately, error detection and correction code uses a substantial portion of a flash EEPROM memory. In fact, some portion of the array is required to store the error detection and correcting bits with each data set in the array. Error detection and correction codes can require a very extensive amount of memory space if a number of different errors in the same data set are to be corrected. In one embodiment, ten bytes of error detection and correction code are used with each data set of 512 bytes allowing detection of six errors, and correction of five errors. Space required to store an equivalent error detection and correction code for what may be less than eight bytes of control information stored for each data set would be prohibitive. Furthermore, a significant increase in hardware or software is required to implement the application of the error detection and correction code to the control data fields. Also important, running an error detection and correction code algorithm requires a significant portion of the operating time of the system. Since the control data may be constantly accessed during the use of the array, to place error detection and correction codes in control fields would slow the read and write operation of the flash EEPROM memory arrays significantly and might render multi-bit storage arrays commercially non-competitive. Because of this, a most essential portion of data stored in flash EEPROM arrays is the control data which allows the various data sets to be properly programmed and retrieved.